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The Path to Future Interconnects
 

Thursday, July 16
10:00am-4:30pm
Moscone North, Hall E, Room 133      SRC logo- SEMICON West 2015    EDS logo- SEMICON West 2015

 
Session Partner: IEEE Electron Devices Society and Semiconductor Research Corporation (SRC)     

The rate of improvement in high performance computing has slowed dramatically. This has been primarily caused by the energy constraints coming from moving data across interconnect networks. The architecture that has driven the exponential growth in computing for over 70 years has led us to this point by requiring data to be transported between processors and memory parts of the system, and more recently also between multiple processing cores on chips.

Evolutionary approaches to address this challenge are increasingly ineffective, and breakthroughs can happen now only with a system-level view, and co-optimization from processing and materials, through devices and circuits, to system architecture.

Our session speakers will describe the nature of the challenges in fundamental materials and processing of current and future interconnects, and their impact on circuit and system requirements. They will also provide a glimpse of possible research directions that could address this challenge with collaboration and revolutionary approaches.

 

Morning Session (10:00am-12:30pm)


10:00-10:05am

 Jon Candelaria- SEMICON West 2015

 

 

Welcome & Opening Remarks

Jonathan Candelaria (Biography)

Director, Interconnect and Packaging Sciences

Semiconductor Research Corporation


10:05-10:15am   



ITRS Update


10:15-10:40am

Mehul Naik- SEMICON West 2015

Interconnect Performance and Yield Challenges for 7 nm and Beyond (Abstract

Mehul Naik, Ph.D. (Biography)

Principal Member of Technical Staff

Applied Materials 


10:40-11:05am

Larry Zhao- SEMICON West 2015

 

 

Challenges and Solutions for Future Cu and Non-Cu Interconnects (Abstract)

Larry Zhao, Ph.D. (Biography)

Technical Director

Lam Research

 

11:05-11:30am

Azad Naeemi- SEMICON West

CMOS Circuit Impact of Interconnects – Cu and Beyond (Abstract)

Azad Naeemi, Ph.D. (Biography)

Associate Professor

Georgia Institute of Technology

11:30-11:55am

Ramakanth Alapati- SEMICON West 2015

3DIC Technology Past, Present and Future (Abstract)

Ramakanth Alapati (Biography)

Director, Packaging Strategy and Marketing

GLOBALFOUNDRIES

 

11:55-12:30pm            


  Speaker Panel, Open Discussion

 

Afternoon Session (2:00pm-4:30pm)


2:00-2:05pm                             

Jon Candelaria- SEMICON West 2015           

Welcome & Opening Remarks

Jonathan Candelaria (Biography)

Director, Interconnect and Packaging Sciences

Semiconductor Research Corporation


2:05-2:30pm


Keren Bergman- SEMICON West 2015

 

 

Silicon Photonic Interconnection Networks for Energy Efficient Scalable Data Movement in High-Performance Computing (Abstract)

Keren Bergman, Ph.D. (Biography)

Professor and Chair of Electrical Engineering

Columbia University

2:30-2:55pm

Azad Naeemi- SEMICON West

 

Interconnects for Emerging 'Beyond CMOS' Devices and Circuits (Abstract)   

Azad Naeemi, Ph.D. 

Georgia Institute of Technology


2:55-3:20pm

Jan Vanfleteren- SEMICON West 2015

 

Interconnects for Flexible/Stretchable Circuits (Abstract)

Jan Vanfleteren, Ph.D. (Biography)

Senior Engineer and R&D Manager

IMEC


3:20-3:45pm

Jan Rabaey- SEMICON West 2015

Lessons from Brain Connectivity (for Future Interconnect Circuits) (Abstract)

Jan Rabaey, Ph.D. (Biography

Professor

UC Berkeley


3:45-4:30pm

Speaker Panel, Open Discussion

 

Please check back frequently for updates and more information as agendas develop and speakers are announced.

 

Registration 

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By June 5

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Non Member (Day Pass)

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